Semiconductor memory circuitry including die sites sized for 256M to 275M memory cells in a 8&#39;&#39; wafer

ABSTRACT

Processes are disclosed which facilitate improved high density memory circuitry, most preferably dynamic random access memory (DRAM) circuitry. In accordance with aspects of the invention, considerably greater numbers of die sites per wafer are achieved for 6 inch, 8 inch and 12 inch wafers for 4M, 16M, 64M and 256M integration levels. Further, a semiconductor memory device includes, i) a plurality of functional and operably addressable memory cells arranged in multiple memory arrays formed on a semiconductor die; and ii) circuitry formed on the semiconductor die permitting data to be written to and read from one or more of the memory cells, at least one of the memory arrays containing at least 100 square microns of continuous die surface area having at least 170 of the functional and operably addressable memory cells.

RELATED PATENT DATA

[0001] This patent resulted from a continuation-in-part application ofU.S. patent application Ser. No. 08/530,661, filed on Sep. 20, 1995,entitled “Semiconductor Memory Circuitry”, listing Brent Keeth andPierre C. Fazan as inventors, and which is now U.S. Pat. No. ______.

TECHNICAL FIELD

[0002] This invention relates to semiconductor memory fabrication at the256M, 64M, 16M and 4M integration levels.

BACKGROUND OF THE INVENTION

[0003] High density integrated circuitry is principally fabricated fromsemiconductor wafers. Upon fabrication completion, a wafer contains aplurality of identical discrete die areas which are ultimately cut fromthe wafer to form individual chips. Die areas or cut dies are tested foroperability, with good dies being assembled into separate encapsulatingpackages which are used in end-products or systems.

[0004] One type of integrated circuitry comprises memory. The basic unitof semiconductor memory is the memory cell. Capable of storing a singlebit of information, the memory cell has steadily shrunk in size toenable more and more cells per area of a semiconductor substrate orwafer. Such enables integrated memory circuitry to be more compact, aswell as faster in operation.

[0005] Example semiconductor memories include ROMs, RAMs, PROMs, EPROMsand EEPROMs. Some emphasize compactness and economy over speed. Othersfocus on lightning-fast operation. Some store data indefinitely, whileothers are so temporary they must be refreshed hundreds of time everysecond. The smallest memory cell comprises the single transistor andsingle capacitor of a dynamic random access memory (DRAM).

[0006] One industry accepted manner of classifying a memory chip is bythe number of final functional and operably addressable memory cellswhich are contained on a single chip. To maximize density, individualcells are arranged in multiple repeating memory arrays. DRAM fabricationhas progressed to the point where millions of functional and operablyaddressable memory cells can be included in a single chip. Maximizingdensity of single transistor and other memory cells is a continuing goalin semiconductor memory fabrication.

[0007] With each new fabricating generation, the number of memory cellsper die has historically increased by a factor or four. For example whatis commonly referred to as the 256K generation (262,144 addressable DRAMcells per chip) led to the 1M generation (1,048,576 addressable DRAMcells per chip). The 1M generation led next to the 4M generation(4,194,304 addressable DRAM cells per chip). The 4M generation led tothe 16M generation (16,777,216 addressable DRAM cells per chip), whichnext led to the 64M generation (67,108,864 addressable DRAM cells perchip). The industry is presently working on the next factor of fourgeneration, referred to as 256M (268,435,456 DRAM cells per chip), whichhas a memory cell pitch of 0.6 micron. Historically with eachgeneration, the number of addressable memory cells per chip increasesexactly by a factor of four with an attendant increase in chip area.However, the increase in chip area has not been directly proportional tothe increase in cells due to improved processing techniques which enablethe individual memory cell size to be shrunk and thereby density toincrease. Nevertheless, each next generation puts four times the numberof memory cells from the previous generation on a single chip.

BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Preferred embodiments of the invention are described below withreference to the following accompanying drawings.

[0009]FIG. 1 is a diagrammatic sectional view of a semiconductor waferfragment.

[0010]FIG. 2 is a view of the FIG. 1 wafer shown at a processing stepsubsequent to that shown by FIG. 1.

[0011]FIG. 3 is a view of the FIG. 1 wafer shown at a processing stepsubsequent to that shown by FIG. 2.

[0012]FIG. 4 is a view of the FIG. 1 wafer shown at a processing stepsubsequent to that shown by FIG. 3.

[0013]FIG. 5 is a view of the FIG. 1 wafer shown at a processing stepsubsequent to that shown by FIG. 4.

[0014]FIG. 6 is a view of the FIG. 1 wafer shown at a processing stepsubsequent to that shown by FIG. 5.

[0015]FIG. 7 is a view of the FIG. 1 wafer shown at a processing stepsubsequent to that shown by FIG. 6.

[0016]FIG. 8 is a view of the FIG. 1 wafer shown at a processing stepsubsequent to that shown by FIG. 7.

[0017]FIG. 9 is a view of the FIG. 1 wafer shown at a processing stepsubsequent to that shown by FIG. 8.

[0018]FIG. 10 is a diagrammatic top view of FIG. 9.

[0019]FIG. 11 is a view of the FIG. 1 wafer shown at a processing stepsubsequent to that shown by FIG. 9.

[0020]FIG. 12 is a view of the FIG. 1 wafer shown at a processing stepsubsequent to that shown by FIG. 11.

[0021]FIG. 13 is a diagrammatic sectional view of another semiconductorwafer fragment.

[0022]FIG. 14 is a view of the FIG. 13 wafer shown at a processing stepsubsequent to that shown by FIG. 13.

[0023]FIG. 15 is a view of the FIG. 13 wafer shown at a processing stepsubsequent to that shown by FIG. 14.

[0024]FIG. 16 is a diagrammatic sectional view of still anothersemiconductor wafer fragment.

[0025]FIG. 17 is a view of the FIG. 16 wafer shown at a processing stepsubsequent to that shown by FIG. 16.

[0026]FIG. 18 is a view of the FIG. 16 wafer shown at a processing stepsubsequent to that shown by FIG. 17.

[0027]FIG. 19 is a diagrammatic sectional view of yet anothersemiconductor wafer fragment.

[0028]FIG. 20 is a diagrammatic top view of FIG. 19.

[0029]FIG. 21 is a diagrammatic sectional view of yet still anothersemiconductor wafer fragment.

[0030]FIG. 22 is a diagrammatic top view of FIG. 21.

[0031]FIG. 23 is a view of the FIG. 21 wafer shown at a processingsequence subsequent to that shown by FIG. 21.

[0032]FIG. 24 is a diagrammatic sectional view of another semiconductorwafer fragment.

[0033]FIG. 25 is a diagrammatic top view of FIG. 24.

[0034]FIG. 26 is a diagrammatic top view of an alternate embodimentlayout.

[0035]FIG. 27 is a perspective diagram illustrating digit line twist orswapping in a vertical plane.

[0036]FIG. 28 is a perspective diagram illustrating alternate digit linetwist or swapping in a vertical plane.

[0037]FIG. 29 is a perspective diagram illustrating further alternatedigit line twist or swapping in a vertical plane.

[0038]FIG. 30 is a perspective diagram illustrating still furtheralternate digit line twist or swapping in a vertical plane.

[0039]FIGS. 31 and 32 are top diagrammatic and schematic views of memorycircuitry layouts.

[0040]FIG. 33 is a diagrammatic sectional view of a semiconductor waferfragment as would be positionally taken along and through the digit lineof FIG. 26.

[0041]FIG. 34 is a perspective view of a semiconductor package.

[0042]FIG. 35 is a diagrammatic view of circuitry layout for asemiconductor memory device.

[0043]FIG. 36 is a top view of a semiconductor wafer fragment comprisinga plurality of semiconductor memory devices in accordance with theinvention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0044] This disclosure of the invention is submitted in furtherance ofthe constitutional purposes of the U.S. Patent Laws “to promote theprogress of science and useful arts” (Article 1, Section 8).

[0045] Implementing memory and other electronic circuitry involvesconnecting isolated devices through specific electric paths. Further, itis necessary to electrically isolate devices built into the substratefrom one another. Electrical isolation of devices as circuit densityincreases is a continuing challenge.

[0046] One method of isolating devices involves the formation of asemi-recessed or fully recessed oxide in the nonactive (or field) areaof the substrate. These regions are typically termed as “field oxide”and are formed by LOCal Oxidation of exposed Silicon, commonly known asLOCOS. One approach in forming such oxide is to cover the active regionswith a thin layer of silicon nitride that prevents oxidation fromoccurring therebeneath. A thin intervening layer of a sacrificial padoxide is provided intermediate the silicon substrate and nitride layerto alleviate stress and protect the substrate from damage duringsubsequent removal of the nitride layer. The unmasked or exposed fieldregions of the substrate are then subjected to a wet H₂O oxidation,typically at atmospheric pressure and at temperatures of around 1000°C., for two to four hours. This results in field oxide growth wherethere is no masking nitride.

[0047] However at the edges of the nitride, some oxidant also diffuseslaterally. This causes the oxide to grow under and lift the nitrideedges. Because the shape of the oxide at the nitride edges is that of aslowly tapering oxide wedge that merges into another previously formedlayer of oxide, it has commonly been referred to as a “bird's beak”. Thebird's beak is a lateral extension or encroachment of the field oxideinto the active areas where the devices are formed. Although the lengthof the bird's beak depends upon a number of parameters, the length istypically 0.15 micron-0.5 micron per side.

[0048] This thinner area of oxide resulting from the bird's beakprovides the disadvantage of not providing effective isolation in theseregions, and as well unnecessarily consumes precious real estate on thesemiconductor wafer. Further, as the circuit density (commonly referredto as minimum device pitch) falls below 1.0 micron, conventional LOCOStechniques fail due to excessive encroachment of the oxide beneath themasking stack. The closeness of the masking block stacks in suchinstances results in effective joining of adjacent bird's beaks, thuseffectively lifting the stacks and resulting in no masking effect to theoxidation.

[0049] This disclosure provides an alternate technique which enables useof a dry, high pressure, O₂ oxidizing ambient for oxidizing conditionsto minimize bird's beak encroachment. This disclosure also provides analternate technique of forming field oxide regions in a manner whichfavorably minimizes bird's beak size. This disclosure also provides analternate technique enabling elimination of field oxide regions betweencertain adjacent memory cells.

[0050] Further, the reduction in memory cell size required for highdensity DRAMs results in a corresponding decrease in the area availablefor the storage node of the memory cell capacitor. Yet, design andoperational parameters determine the minimum charge required forreliable operation of the memory cell despite decreasing cell area.Several techniques have been developed to increase the total chargecapacity of the cell capacitor without significantly affecting the cellarea. These include structures utilizing trench and container-shapedstacked capacitors.

[0051] This disclosure provides an alternate technique which enablescapacitance to be maximized within a given area. This disclosure alsoprovides an alternate technique enabling closer mask opening tolerancesby reducing mask misalignment spacing between adjacent devices.

[0052] The area on a substrate consumed by memory integrated circuitryis impacted by the number of conductive layers which are provided forproducing the circuitry. Generally, the lower the number of conductiveline layers, the simpler the process but the greater the area consumedby the memory cell. The substrate area consumed by the memory cells canbe reduced by providing more conductive line layers, but at the expenseof process complexity.

[0053] This disclosure provides an alternate technique of using acomparatively larger number of conductive line layers enabling takingfull advantage of the elimination of field oxide regions between certainadjacent memory cells as alluded to above.

[0054] One or more of the above described techniques, or othertechniques, can be utilized in the production of 64M, 16M or 4M memorychips in accordance with the invention, with the invention only beinglimited by the accompanying claims appropriately interpreted inaccordance with the doctrine of equivalents.

[0055] The discussion initially proceeds with description of processesfor forming field oxide regions in manners which minimize bird's beakencroachment into substrate active ares. FIG. 1 illustrates asemiconductor wafer fragment in process for formation of a pair ofadjacent field oxide regions having a minimum pitch of less than orequal to 0.7 micron, and is indicated generally with reference numeral10. Such is comprised of a starting bulk semiconductor silicon substrate12. A sacrificial pad oxide layer 14 is thermally grown oversemiconductor substrate 12 to a thickness of from 20 Angstroms to 100Angstroms. A masking layer 15, preferably Si₃N₄, is provided oversacrificial pad oxide layer 14 to a thickness of from 500 Angstroms to3000 Angstroms. The function of layer 14 is to cushion the transition ofstresses between silicon substrate 12 and nitride layer 15. Nitridelayer 15 will function as the masking layer for ultimate formation ofthe field oxide regions.

[0056] Referring to FIG. 2, first nitride layer 15 has been patternedand etched as shown to form nitride masking blocks 16, 17 and 18. Achannel-stop implant can be conducted prior to removing the illustratedmasking blocks. The etch to produce nitride blocks 16, 17 and 18 issubstantially selective to oxide layer 14. However, the etch does resultin removal of a portion of pad oxide layer 14 in an uneven manner due inpart to the inherent preferred thinness of layer 14. Blocks 16, 17 and18 are provided to define and thereby overlie desired active arearegions on the substrate. The illustrated masking blocks provide anexample preferred minimum pitch 20 of adjacent blocks of less than orequal to 0.7 micron, with 0.6 being a specific example.

[0057] Referring to FIG. 3, the wafer is preferably subjected to a wetisotropic etch to remove remaining portions of exposed sacrificial oxidelayer 14 from the substrate. This also produces undercut etching oflayer 14 beneath nitride blocks 16, 17 and 18, as shown.

[0058] Referring to FIG. 4, the wafer is subjected to oxidizingconditions to grow a preferred second sacrificial oxide layer 13 havinga thickness of from 60 Angstroms to 120 Angstroms. Layer 13 willfunction as a silicon etch stop, as will be apparent subsequently. Thethickness of layer 13 has an effect on the resultant bird's beak size.The thicker layer 13, the larger will be the bird's beak size afterfield oxidation.

[0059] Referring to FIG. 5, a layer 30 of silicon is provided overpatterned masking nitride blocks 16, 17 and 18, and over secondsacrificial oxide layer 13. A preferred material for layer 30 ispolysilicon deposited to a thickness ranging from 200 Angstroms to 1000Angstroms. Alternate materials, by way of example only, includeamorphous silicon and porous silicon. Subsequently, a second maskinglayer 32 is provided over silicon layer 30 also to a preferred thicknessof from 200 Angstroms to 1000 Angstroms. Layer 32 preferably constitutesa material which is selectively etchable relative to underlying siliconmaterial 30. Example preferred materials include SiO₂ and Si₃N₄, withSiO₂ being more preferred. The thickness of layer 32 is used to set thelength of the foot portion independent of the first spacer height, aswill be apparent subsequently.

[0060] Referring to FIG. 6, second masking layer 32 is anisotropicallyetched to define pairs 33, 34 and 31 of second masking layer sidewallspacers over silicon layer 30, and to outwardly expose portions ofsilicon layer 30. The anisotropic etch is preferably conductedselectively relative to silicon layer 30, as shown. Pairs 33, 34 and 31of second masking sidewall spacers define interconnected respectivepairs 35, 36 and 37 of respective masked laterally opposed and outwardlyprojecting foot portions of silicon layer 30.

[0061] Referring to FIG. 7, exposed portions of silicon layer 30 areanisotropically etched selectively relative to second sacrificial oxidelayer 13 to form respective pairs 38, 40 and 42 of silicon sidewallspacers. Silicon sidewall spacer pair 38 includes laterally opposed andlaterally outward projecting foot portion pair 35. Silicon sidewallspacer pair 40 comprises laterally opposed and laterally outwardprojecting foot portion pair 36. Silicon sidewall spacer pair 42includes laterally opposed and laterally outward projecting foot portionpair 37.

[0062] Referring to FIG. 8, second masking layer sidewall spacers 33, 34and 31 are stripped from the substrate. Alternately, these spacers canremain at this point in the process and be stripped after fieldoxidation. Further as an alternate, spacers 33, 34 and 31 might remainafter field oxidation. Most preferred is removal of such spacers now asshown in FIG. 8.

[0063] Referring to FIG. 9, the wafer is subjected to oxidizingconditions which oxidizes the silicon of bulk substrate 12 and siliconsidewall spacers 38, 40 and 42 to form the illustrated pair 44 and 45 offield oxide regions. Any of a number of oxidizing conditions might beused. One example includes oxidizing in an O₂ ambient at a pressure ofat least 15 atmospheres. The atmosphere will preferably be essentiallyvoid of H₂O during the oxidizing, and constitutes essentially pure O₂ orO₂ injected into the reactor in combination with a carrier gas, such asN₂ or Ar. The preferred upper pressure limit for such an oxidation is 50atmospheres, with 25 atmospheres being a more preferred condition. Thepreferred temperature range during such an oxidation is from 950° C. to1300° C. Growth rate in such a dry oxygen ambient at 25 atmospherespressure at 1000° C. is 4000 Angstroms per 70 minutes. Such oxidation ispreferably conducted to provide field oxide regions 44 and 45 to have alocation of maximum thickness of from 1500 Angstroms to 3000 Angstroms.As depicted, field oxide regions 44 and 45 define substrate active area25 therebetween. During field oxidation, a very thin layer of oxide(20-200 Angstroms, and not shown) may form atop masking blocks 16, 17and 18 from transformation of the Si₃N₄ to SiO₂.

[0064] Also during oxidation, silicon sidewall spacers 38, 40 and 42,being of a silicon material similar to substrate 12, are also oxidizedand grow in volume to approximately twice their original size. Thisresults in formation of what is referred to as “Mickey Mouse” ears 46.However, the preferred 200 Angstroms to 1000 Angstrom thin nature ofsilicon layer 30 which ultimately forms silicon spacers 35, 36 and 37results in smaller (thinner) “Mickey Mouse” ears 46. This provides thesubsequent advantage of minimizing upper topography of the resultantfield oxide regions. Further, the elongated nature of foot portions 35,36 and 37 (FIG. 8) advantageously provides adequate lateral displacementto prevent significant oxygen encroachment to minimize bird's beakformation beneath nitride blocks 16, 17 and 18.

[0065]FIG. 10 illustrates a diagrammatic top view of FIG. 9 emphasizingthe illustrated field oxide regions 44 and 45, and active area 25therebetween. A staggered layout of the active area regions ispreferably utilized, with pitch 20 being the minimum pitch between themost closely adjacent field oxide regions. The staggering produces awider pitch 21 (FIG. 10 only) between further spaced adjacent fieldoxide regions, as shown. During field oxidation, the location of maximumfield oxide thickness typically occurs centrally relative to therespective widths of the regions along the wider pitch line 21. Fieldoxide thickness is typically less along pitch line 20, where substratestress is greater due to closeness of the adjacent nitride masks.

[0066]FIG. 11 illustrates stripping of first masking layer materialblocks 16, 17 and 18 from the substrate, and subsequent stripping ofsecond sacrificial oxide layer material 13. Further, essentially anyremnants of first sacrificial oxide layer 14 which might be remainingwould also be removed. In the course of such removals, any oxide formedatop blocks 16, 17 and 18 would be removed, resulting in removal ofoxide from atop field oxide regions 44 and 45 in a quanta of from 50Angstroms to 250 Angstroms. Further, removal of layer 13 will preferablyremove an additional 50 Angstroms to 500 Angstroms of oxide from thefield regions. Such also advantageously results in reduced ears 46 a.Subsequently, a third sacrificial oxide layer 48 is preferably grown(i.e., from 150 Angstroms to 350 Angstroms over the silicon substrate)to eliminate the undesired formation of the silicon-nitride during thefield oxidation (commonly referred to as the “Kooi effect”). Such oxidegrowth results in an estimated growth of field oxide regions 44 and 45of from 50 Angstroms to 200 Angstroms.

[0067] Referring to FIG. 12, third sacrificial oxide layer 48 isstripped from the substrate. Such also etches from 200 Angstroms to 400Angstroms of field oxide regions 44 and 45, and desirably has the effectof essentially eliminating the remaining sharp points 46 a to produce anupper smooth topography for such field oxide regions. Thus, bird's beakencroachment into active area is minimized. Field oxide regions 44 and45 might also alternatively be provided to be recessed relative to bulksubstrate 12.

[0068] The discussion next proceeds regarding improved techniques forroughening polysilicon surfaces for use in enhancing capacitance incapacitor constructions. More particularly and initially with referenceto FIGS. 13-15, a semiconductor wafer fragment in process is indicatedgenerally with reference numeral 50. Such comprises a bulk semiconductorsubstrate 52 (typically p-doped monocrystalline silicon) having ann-type diffusion region 54 provided therein. Diffusion region 54comprises a node to which electrical connection to a capacitor plate isto be made. A layer 56 of insulative silicon dioxide is provided overbulk substrate 52, and provided with a container opening 58 therein todiffusion region 54. The wafer is placed within a chemical vapordeposition reactor, and a layer 60 of in situ conductively dopedamorphous silicon is chemical vapor deposited over the depictedsubstrate at a first temperature, which is below 600° C.

[0069] An example preferred process for providing layer 60 would be toplace the wafer in a six liter reactor with the wafer maintained at 560°C. and a reactor pressure at 80 Torr. SiH₄ and phosphine are fed to thereactor at respective flow rates of 500 sccm and 300 sccm for 400seconds. Such will produce a layer 60 having a thickness ofapproximately 1,000 Angstroms. By way of example only, disilane could besubstituted for SiH₄ at a flow rate of 300 sccm while the otherparameters remain constant. Such will produce layer 60 to approximately1,000 Angstroms in 15 seconds. For purposes of the continuingdiscussion, doped amorphous silicon layer 60 has an outer surface 62 ofa first degree of roughness.

[0070] Referring to FIG. 14, the substrate temperature within thereactor is raised at a selected rate to an annealing second temperaturewhich is between 550° C. and 950° C. The substrate is maintained at thesecond annealing temperature for a period of time sufficient to convertdoped amorphous silicon layer 60 into a doped polysilicon layer 65having an outer surface 64 of a second degree of roughness which isgreater than the first degree of roughness. Substrate 50 is not removedfrom the reactor nor exposed to any oxidizing conditions between thetime of deposition of amorphous silicon layer 60 and its conversion topolysilicon layer 65.

[0071] The selected ramp rate for the temperature increase is preferablyless than or equal to 10° C./sec. Ramp rates of 30° C. and 40° C. werealso utilized and while a roughness increase of surface 62 to surface 64was observed, the increase was not as significant as where the ramp ratewas kept at a lower rate of at or below 10° C./sec. The annealing secondtemperature is also kept at preferably below 700° C. to minimize thethermal budget on the wafer during processing.

[0072] The reactor ambient during the annealing process is preferablykept at a vacuum pressure. Alternately, an inert atmosphere of forexample N₂ can be utilized. Preferably, the reactor pressure during theamorphous silicon deposition and annealing steps is the same pressure,with such being greater than 0.01 Torr. Where an inert gas is providedwithin the reactor during the annealing step, reactor pressures ofgreater than or equal to 760 Torr can be utilized.

[0073] Example actual anneals were conducted at wafer temperatures of650° C., 660° C., 670° C., 680° C., 700° C., 750° C., 800° C. and 850°C. Reactor pressures were varied from 400 mTorr to 80 Torr with andwithout N₂. Deposition times ranged from 30 seconds to 900 seconds.Temperature ramp rates between the amorphous silicon deposition and theannealing ranged from 4° C./sec to 10° C./sec. The best results atproducing maximized surface roughness of surface 64 as compared tooriginal surface 62 occurred at 670° C. for between 30 and 60 seconds,where the ramp rate between deposition and anneal was approximately 5°C./sec.

[0074] Such a resultant surface is advantageously used in the formationof improved capacitor constructions in memory circuitry. FIG. 15illustrates a dielectric layer 67 and subsequently deposited outercapacitor plate 68 (conductively doped polysilicon) provided to completeformation of a capacitor construction 59.

[0075] FIGS. 16-18 illustrate an alternate embodiment construction andprocess which incorporates at least one additional process step overthat depicted by FIGS. 13-15. Like numbers from the FIGS. 13-15embodiment are utilized where appropriate, with differences beingindicated with the suffix “a” or with different numerals. FIG. 16illustrates the same essential FIG. 13 wafer fragment 50 a incorporatingadditional features and at a subsequent processing step to that shown byFIG. 13. Specifically and after provision of in situ doped amorphoussilicon layer 60, the substrate temperature is raised at a selected rateto an intermediate silicon seeding temperature. At the seedingtemperature, a discontinuous layer of silicon particles 69 is providedatop doped amorphous silicon layer 60. This occurs within the samereactor and without any intervening exposure of the wafer to oxidizingconditions between the time of amorphous silicon deposition andprovision of the discontinuous seeding particles. The seeds constitutediscrete clusters of silicon atoms.

[0076] A preferred process for providing the silicon particles is tofeed a silicon source gas to the reactor which comprises a gaseouscompound of the formula Si_(n)H_(2n+2), where “n” is an integer greaterthan or equal to 1. An example process in accordance with the abovedescribed embodiment would be to feed disilane gas to the reactor at arate of 5 sccm to 10 sccm for from 30 to 60 seconds. Preferably,discontinuous silicon particles 69 are provided to have a particlediameter of from 10 Angstroms to 50 Angstroms. An example seedingtemperature is 600° C., with the selected first ramp rate to the seedingtemperature being at or below 10° C./sec. The silicon seedingtemperature is preferably at or below 600° C. The result is productionof an inherently rougher outer surface 62 a than layer 62 of theprevious embodiment.

[0077] Referring to FIG. 17, the substrate again within the samechemical vapor deposition reaction and without any intervening exposureof the wafer to oxidizing conditions, has its temperature raised at asecond selected rate to the annealing temperature which is between 550°C. and 950° C. Again, the preferred rate is at or below 10° C./sec. Thesubstrate is maintained at the annealing temperature for a period oftime sufficient to convert the doped amorphous layer into a dopedpolysilicon layer 65 a having outer surface 64 a, with such outersurface having a second degree of roughness which is greater than thefirst degree of roughness of amorphous silicon layer outer surface 62 a.

[0078] An advantageous phenomenon occurs in utilization of siliconparticles 69. The amorphous silicon of layer 60 migrates on surface 62 aand agglomerates onto the silicon seeds/particles 69, creating bumps andvalleys and therefore an outer polysilicon surface having even greaterroughness. FIG. 17 depicts the particles 69 as being discrete at theconclusion to the annealing processing step. More typically, suchparticles would no longer exist as discrete particles, and would ratherconstitute a part of the homogeneously formed polysilicon crystallattice of layer 65 a. An example annealing temperature wherein asilicon seeding temperature of 600° C. is utilized would be 630° C. Alsopossible in accordance with the invention, the annealing temperature andseeding temperature might be the same temperature, such that the secondselected temperature ramp rate is 0° C./sec.

[0079] Referring to FIG. 18, a capacitor dielectric layer 67 a and cellplate layer 68 a are provided to produce a resultant capacitorconstruction 59 a. Layers 67 a and 68 a will have slightly greaterroughness than the first described embodiment due to the enhancedroughening produced by the silicon seeding process.

[0080] One additional problem associated with density maximization ofmemory circuitry concerns required spacing which is provided betweenadjacent devices, such as between a bit line contact and a capacitorconstruction. The problem is best understood with reference to FIGS. 19and 20.

[0081]FIG. 19 illustrates a semiconductor wafer fragment comprising apair of DRAM container capacitor constructions 72 and 74 having a bitcontact plug 75 extending vertically therebetween. Other typical circuitcomponents, such as field oxide regions, bulk substrate and an overlyingbit line are not shown or described as such are not particularlypertinent to the points here being made. Each capacitor 72, 74 is formedwithin a respective container opening 76 within a previously providedinsulating dielectric layer. Each comprises a storage node plate 78 andan overlying capacitor dielectric layer 80. A capacitor cell plate,common to both capacitors, is typically provided in the form of anelectrically conductively doped polysilicon layer 82. Layer 82effectively comprises a sheet as-deposited, with essentially all cellplates of the capacitors being electrically connected to or constitutinga part of this sheet.

[0082] However, contact openings or holes are cut through the sheet atcertain locations to enable electrical connection with areas lower inthe substrate, such as for the illustrated bit plug 75. Such isaccomplished by providing an opening in sheet 82, as is depicted by amask opening outline 84. Subsequently, a bit contact 86 is providedlaterally within the confines of sheet opening 84. Accordingly, theresultant bit line plug 75 will be effectively electrically isolatedfrom cell plate 82.

[0083] The above illustrated openings 76, 84 and 86 are provided bythree different and separate photolithographic masks. Due to thepossibility of mask misalignment, tolerance for mask misalignment mustbe provided relative to each mask such that certain masks will notoverlap with one another. For example, spacing “x” provides for an areafor relative misalignment of the masks to produce openings 84 and 86relative to one another. Further, spacing “y” is provided to assuremisalignment tolerance for the storage node 76 container etch verses thecell plate sheet opening 84 etch. Typically, the misalignment tolerancefor both spacings “x” and “y” is 0.15 micron, providing for a truespacing between bit plug 75 and storage node layer 78 of 0.3 micron.However, 0.3 micron is more than what is required to provide sufficientelectrical isolation between the contact plug and the adjacentcapacitors, resulting in greater real estate being consumed for a pairof adjacent memory cells that is otherwise required.

[0084] Such extra spacing can be overcome to a degree in a mannerdescribed with reference to FIGS. 21-23. Like numerals from the FIGS. 19and 20 embodiment are utilized where appropriate, with differences beingindicated by the suffix “b”, or with different numerals. Specifically,the lateral or horizontal misalignment tolerance between the respectivecontainer openings 76 and the adjacent sheet contact opening 84 arereduced on each side of bit plug opening 86 by a factor of the “y”spacing. Thus in connection with the described embodiment, the adjacentpair of containers 76 can be placed 0.3 micron closer to one another,thus increasing circuit density. Such is essentially accommodated for byallowing or providing for the misalignment tolerance of spacing “y” tobe in a vertical direction as opposed to a horizontal direction.

[0085] Specifically, capacitor storage node containers 78 b are recessedrelative to the upper surface of the container dielectric layer at leastby the misalignment tolerance distance “y”. Thereby, true maskmisalignment tolerance for mask opening 84 is equal to twice the sum ofthe thicknesses of capacitor cell plate layer 82 and dielectric layer80. FIG. 21 illustrates essential perfect alignment of mask opening 84relative to the distance between containers 76, with mask opening 84corresponding in lateral expanse to the distance between the closestdistance between container openings 76.

[0086]FIG. 21 illustrates an example etch of 82 which would otherwiseoccur if an anisotropic etch were conducted through mask opening 84relative to cell plate layer 82. However as shown in FIG. 23, the etchthrough mask opening 84 is conducted to be isotropic. This will undercutetch layer 82 beneath the photoresist to cause further displacement ofthe edge of cell poly layer 82 relative to the edge of bit contactopening 86. Thus adequate “x” and “y” misalignment spacing is providedrelative to the storage node, sheet opening and bit line contacts byextending the “y” misalignment tolerance substantially vertically asopposed to horizontally. There will be an associated loss in capacitancedue to recessing of storage node capacitor plates 78 b, whicheffectively shrinks the size of plates 78 b.

[0087] Example integration of one or more of the above processes isdescribed with reference to FIGS. 24 and 25. Such illustrate asemiconductive wafer fragment 90 comprised of a bulk substrate 92 andfield oxide regions 94. Preferably, field oxide regions 94 are producedin accordance with the above described processes to minimize bird's beakencroachment. The area between field oxide regions 94 constitutes activearea 95. A series of four word lines 96, 97, 98 and 99 are illustratedin FIG. 24. Each is comprised of a composite of five layers, namely, agate oxide layer, a conductively doped polysilicon layer, a WSi_(x)layer, an oxide layer, and a Si₃N₄ capping layer. Electricallyinsulative sidewall spacers, typically formed of Si₃N₄, are alsoprovided relative to the respective word lines, as shown.

[0088] An insulating dielectric layer 100, typically borophosphosilicateglass (BPSG), is provided outwardly of the illustrated word lines. Apair of container capacitor constructions 102 and 104 is provided asshown. An intervening bit contact plug 106 extends vertically betweencapacitors 102 and 104. The illustrated construction constitutes twomemory cells of a DRAM array, with such cells sharing a bit contact andan intervening substrate diffusion region (not shown). Contacts 107,108, and 109 for the respective components to bulk substrate 92 areprovided as shown.

[0089] Each capacitor 102, 104 is preferably constructed by acombination of the processes provided above. For example, each comprisesa storage node 110 constituting conductively doped polysiliconpreferably deposited to have a rough outer surface as described above.Further, each storage node layer 110 is preferably recessed relative tothe outer surface of insulating dielectric layer 100 to enable thelateral expanse of the wafer consumed by mask misalignment tolerance tobe reduced as described above. Such facilitates placing of capacitors102, 104 and bit contact 106 closer to one another. A capacitordielectric layer 112 and outer conductive cell polysilicon layer 114 areprovided as shown.

[0090] An insulating dielectric layer 116, typically BPSG, is providedoutwardly of capacitor constructions 102 and 104. Bit contact plug 106is provided therethrough and through insulating dielectric layer 100 tobit contact 108. Bit plug 106 preferably comprises the illustratedcomposite of layer 118 of titanium, layer 120 of TiN as a barrier layer,and layer 122 of elemental tungsten. Where layer 118 interfaces withbulk silicon substrate 92, a conductive WSi_(x) forms.

[0091] Insulating dielectric layer 116 is provided with a planarizedouter surface atop which a digit line 124 is provided. Such isillustrated as a simple line in FIG. 25 for clarity. Digit line 124would typically comprise a composite of a lower adhesion layer 126 oftitanium, a bulk mass conductive layer 128 of aluminum or an aluminumalloy, and an outer anti-reflective coating layer 130 of TiN. In thisdescribed embodiment, all digit lines of the array would be provided atthe same essential level as digit line 124.

[0092] Another insulating dielectric layer 132 is provided outwardly ofbit line 124, and provided with a planarized outer surface. Compositepatterned electrically conductive runners 136 are shown outwardly oflayer 132 (FIG. 24). Such conductive runners typically are not utilizedas part of the DRAM memory array, but are utilized in the pitch and theperipheral circuitry of such arrays.

[0093]FIG. 25 illustrates, by dashed outline 140, the area which isconsumed by a single memory cell in accordance with this embodiment.Such area can be considered or described as relative to a minimumcapable photolithographic feature dimension “F”. As shown, a singlememory area 140 is 4F wide by 2F deep, thus providing a consumed areafor a single memory cell of 8F².

[0094] The FIG. 24 circuit constitutes a die which is fabricated toinclude four composite conductive line layers. The first of those layersconstitutes composite word lines 96, 97, 98 and 99 which arecollectively formed from the same essential processing steps. The secondcomposite conductive line layer constitutes cell plate polysilicon layer114. Within the memory array, such a layer can be considered asconstituting a sheet through which isolated waffle-like openings (i.e.,the openings 84 of the previous described embodiment) are provided forprovision of isolated bit plugs 106 therethrough. Yet in the area of theperipheral circuitry or the pitch circuitry to the memory array, layer114 would be patterned to form one or more conductive lines to providedesired electrical interconnection.

[0095] The third composite conductive line layer constitutes digit lines124, while the fourth conductive line layer constitutes the compositeperipheral conductors 136.

[0096] This disclosure further provides an alternate process whichenables elimination of field oxide regions within the memory array, thusfacilitating greater circuit density. As background, field oxide regionsprovide electrical isolation between certain adjacent banks of memorycells within the array. Field oxide by definition defines breaks in theactive area formed within the bulk substrate between adjacent cells. Forexample, see FIG. 25 which shows a break between the two adjacent activearea regions 95. Such results from field oxide formed therebetween, withthe illustrated word lines 99 and 96 running atop such field oxideregion for gating a staggered set of memory cells within the array. Thelateral expanse of the field oxide and word lines 96 and 99 for thestaggered active area array constitute circuit area which is consumed ona semiconductor substrate. Specifically, each memory cell of a DRAMarray has 1.5 times the minimum photolithographic feature size, F, ofits lateral expanse consumed by field oxide and area for word lines 96and 99. In accordance with one preferred aspect of this disclosure,memory cell area devoted to electrical isolation from an adjacent celland to word lines 96 and 99 can be reduced from 1.5F to 0.5F.

[0097] Specifically, FIG. 26 illustrates a continuous active area 295formed within the bulk substrate relative to the associated overlyingbit line 224. A series of capacitor contacts 207 and a series of bitline contacts 208 are formed relative to continuous active area 295.Word line pairs 297 and 298 share an intervening bit contact of adjacentpairs of memory cells, which in turn share a diffusion region in thebulk substrate. Electrical isolation between the adjacent pairs ofmemory cells is provided by intervening isolating conductive lines 225which are formed in conjunction with the formation of word lines 297 and298. Lines 225 in operation are connected with ground or a suitablenegative voltage, such as V_(ss) or V_(BB), and effectively substitutefor the electrical isolation formerly provided by field oxide.

[0098] The elimination of field oxide also enables elimination ofconventional active area stagger within the array, thus eliminating areaconsumed by word lines 96 and 99 of the FIG. 25 embodiment. Thus the 4Flateral expanse consumed by a memory cell of FIG. 25 is capable of beingreduced to 3F in the FIG. 26 embodiment (See dashed outline 240 in FIG.26). This result sin the area consumed by a single cell of 6F², ascompared to the 8F² of the FIG. 25 embodiment.

[0099] However, bit line circuitry requirements and associated bit linespacing also play a role in the ability to shrink individual memory cellarea within an array to a 6F² level. Specifically, an actual bit line ordata line structure is comprised of a pair of digit lines, namely D andD* (also referred to as “digit bar”), which connect with a single senseamplifier. Prior to the 256K memory cell level integration, D and D* ranin two separate, but adjacent, arrays with sense amplifiers beinginterposed between the arrays. This arrangement later came to bereferred to as “open architecture”. However once DRAMs reached 256Kdensity, the open architecture proved to be inadequate because of poorersignal to noise.

[0100] As a result, “folded bit line architecture” and improved celldesigns were developed to overcome an unacceptable noise level. With afolded architecture, D and D* run sided by side in common horizontalplanes, but swap horizontal positions at various locations within asingle array, thus producing a noise canceling effect.

[0101] However with a smaller memory cell size of 6F² or lower beingavailable, the space consumed by D and D* and their associated circuitrybecomes a limiting barrier to the 6F² size. In accordance with anotherpreferred aspect of this disclosure, D and D* are fabricated to lieadjacent one another in common vertical planes to facilitate foldedarchitecture and density maximization.

[0102] For example, FIG. 27 illustrates one embodiment of a verticalthree level twist or swap design of D and D* to facilitate achievingpreferred equal bit line lengths running on the upper and lower levelsof the design. As illustrated on the left side of FIG. 27, a digit Dline 310 is on Level 1, while a complementary digit D* line 312 is on aLevel 2 and directly beneath D line 310. D line 310 drops down to Level2 at 314, then to a Level 3 where it is routed around the D* line by aconductive area 316, and is then elevated back up to Level 2 at 315.Accordingly, D line 310 has achieved a twist or a swap in the verticaldirection, or Z-axis, from Level 1 to Level 2. A similar verticaltwisting or swapping occurs for D* line 312. It drops down from Level 2to Level 3, is routed around D line 310 and area 316 by a conductivearea 318, and is then elevated to Level 2 at 313 and ultimately to Level1 at 322. Accordingly, the twisting or swapping is relatively to the “z”direction, with attendant “x” and “y” area being consumed on Level 3 forareas 316 and 318.

[0103]FIG. 28 shows an alternate four level twist or swappingconfiguration. A conductive path 319 is provided at a sub-Level 4. Level4 might comprise a substrate implant, polysilicon, metal, etc. Formationof a transistor from regions 316 and 319 is however highly undesirable.

[0104]FIG. 29 shows an alternate three level configuration. As shown,the twisting or swapping of D line 310 and D* 312 occurs relative toLevel 2 and Level 3 within Level 1.

[0105]FIG. 30 shows another alternate configuration. Digit line D 330 ismoved down one level to 336 via 332 and 334, while D* is twisted upwardto 340 via 342. Region 342 extends outward in the x-y plane, while Dline 330/336 stays in the same x-y configuration. Region 342 alsoextends into or within the vertical plane of an adjacent pair of digitlines D 346 and D* 348. To accommodate this extension of region 342, thebottom D* line 348 is moved to Level 3 along a region 350, and thenbrought back up to Level 2.

[0106]FIG. 31 is a rough diagrammatic view of a preferred memory array.The horizontal running lines principally comprise pairs of D and D*digit lines, with each pair extending relative to a shared senseamplifier 370. A series of word lines 373 extend from respective rowdecoders 372. Intervening electrically conductive isolation lines 374are provided as shown, and connect relative to a common grounding nodeline 376 between the upper and lower illustrated sections of a memoryarray.

[0107] For ease of illustration in FIG. 31, the digit line pairs feedingthe respective sense amps 70 appear as if they were horizontally spacedside-by-side relative to one another. In actuality, the subject digitline pairs are vertically oriented relative to one another in accordancewith the above preferred described embodiments. For example with respectto the top illustrated pair on FIG. 31, a digit D line 360 and a digitD* line 364 are illustrated. Twisting or swapping relative to a verticalplane is indicated by the “x” crossing at location 368. Other staggeredswapping of the other pairs are also shown. Most desirably, each line ofeach pair spends 50% of its length on each of the top and bottom portionof the vertical aligned orientation.

[0108] Referring to FIG. 32, a layout for a portion of a DRAM arrayhaving the preferred double-layer twisted digit lines is depicted. Sixdigit line pairs (DP0, DP2, DP2, DP3, DP4 and DP5) are shown in thisabbreviated layout. Each pair consists of a D line and D* line alignedin a common vertical plane. The uppermost digit lines and lowermostdigit lines are depicted as being of different widths for clarity in thedrawings. In reality, they would be of the same width. The illustrateddashed rectangles comprise active area, with numerals 381 denoting bitcontacts thereto. Lines 382 comprise word lines, while lines 383 areisolation lines substituting for field oxide as described above.Vertical contact vias (CV) are represented by the squares marked with an“X”.

[0109] In the depicted portion of the array, digit line pairs DP0, DP2and DP4 undergo the preferred twist or swap within region 371 by S1, CV3and CV4, and by S2, CV1 and CV2. Digit line pairs DP1, DP3 and DP5 areuntwisted in this portion of the array. The alternating twist patternnot only provides for efficient reduction of capacitive coupling betweenadjacent digit line pairs, but it also provides room for the twistingoperation.

[0110] It will be noted that portions of first conductive strip S1 andsecond conductive strip S2 are vertically aligned with portions ofadjacent digit line pairs. This is possible because first and secondconductive strips S1 and S2 are not on level with either of the adjacentdouble-layer digit lines. The interconnect pattern could be any of thepatterns as depicted by FIGS. 27-31, or different patterns.

[0111] With the vertical twist or swap embodiment, the signal to noiseratios are kept acceptably low. Most preferably, the verticalarrangement and the crossing digit lines are provided to allow for equaltop and bottom orientation and access to the appropriate memory cells.Additionally, the adjoining digit pair of lines are also switchedappropriately to diminish signal to noise problems. Further, thevertical plane swapping facilitates 6F² or smaller memory cell size.

[0112] Preferably, the twisting locations in the array are at quartermarks, either the first and third quarter, or at the halfway mark in thearray. This allows for different digit line pair arrangements to belocated next to each other. Further, the memory cells may be locatedbetween, along side, on top, or underneath the bit lines, thusaccommodating for trench, stacked, or elevated designs.

[0113]FIG. 33 is an example cross sectional view of a wafer fragment 390as would be positionally taken through and along the bit line of FIG.26. It is similar to FIG. 24 but for two notable exceptions. Likenumerals from FIG. 24 are utilized where appropriate with differences ofany significance being indicated with different numerals. The firstnotable exception is absence of field oxide regions within the array,with conductive isolation lines 383 substituting therefor. Word lines ofthe array are designated with numerals 382.

[0114] The second notable exception concerns provision of the digit lineas two composite lines, namely D line 394 and D* line 395 separated byan insulating dielectric layer 393. Each composite digit line ispreferably of the same construction as composite line 124 of FIG. 24. Aninsulating dielectric layer 397 overlies composite D* line 395intermediate patterned lines 136. Thus in this described embodiment, thecircuitry constitutes a die which is fabricated to include fivecomposite conductive line layers. The first of those layers constitutescomposite lines 382 and 383 which are collectively formed in the sameessential processing steps. The second composite conductive line layerconstitutes cell plate polysilicon layer 114, which is patterned to formlines in the area peripheral to the array.

[0115] The third and fourth composite conductive line layers constituteD and D* 394 and 395, respectively. The fifth conductive line layerconstitutes the composite peripheral conductors 136.

[0116] The above described constructions are advantageously utilized toproduce semiconductor memory devices, such as depicted in FIGS. 34 and35. Specifically, a semiconductor die 150 (FIG. 35) is encapsulated in apackage 152 (FIG. 34). Such is shown in the form of a dual in-linepackage (DIP) constituting a ceramic encapsulating body 154 having aseries of electrically conductive interconnect pins 156 extendingoutwardly therefrom (FIG. 34).

[0117] Die 150 (FIG. 35) is comprised of a series of 64 multiple memoryarrays 160 arranged as shown. The area immediately surrounding therespective array areas 160, such as the illustrated areas 162, containwhat is referred to as pitch circuitry, as such circuitry is “on pitch”with the conductive lines which extend outwardly from the associatedmemory arrays 160. Such pitch circuitry 162 would comprise, for example,sense amplifier circuitry, equilibration circuitry, bias devices, I/Odecoders, and other circuitry.

[0118] Die areas 164, 166, 168, 170, 172 and 174 constitute what isreferred to as peripheral circuitry. Pitch circuitry areas 162 wouldelectrically connect with the peripheral circuitry areas, with theperipheral circuitry electrically interconnecting with the illustratedseries of bond and probe pads 175. Suitable wires or other means wouldbe utilized to connect with bond pads 175 to provide electricalconnection to pins 156 of FIG. 34. The peripheral circuitry wouldpreferably include the operably interconnected control and timingcircuitry, address and redundancy circuitry, data and test pathcircuitry, and voltage supply circuitry which collectively enable fullaccess to all addressable memory cells of the memory arrays. Forexample, peripheral circuitry region 164 would typically comprise globalcolumn decode and column addressing circuitry. Section 174 could includesection logic, DC sense amps and write drivers. Peripheral circuitryregions 170 and 172 would include power amplifiers, power busing andchip capacitors. Regions 166 and 168 would include other logiccircuitry.

[0119] One or more of the above described processes and dieconfiguration can facilitate formation of 64M, 16M, and 4M memory die ordevices having smaller size or consumed monolithic die area than hasheretofore been practically achieved. For example, at a 64M memory cellintegration level, a total of no more than 68,000,000 (typically exactly67,108,864) functional and operably addressable memory cells arearranged within collective multiple memory arrays 160. The occupied areaof all of the functional and operably addressable memory cells on thedie consumed within the multiple memory arrays will have a totalcombined area which is no greater than 53 mm².

[0120] In accordance with standard semiconductor memory fabrication, therespective memory arrays are provided with redundant memory cells whichafter test can be operably fused to replace inoperable memory cellscreated during fabrication. Where an inoperable memory cell isdetermined during tests, the entire respective row (word line) or column(bit line) is fused out of operation, and a substitute operableredundant row or column substituted in its place. Accordingly duringfabrication, the individual respective memory arrays, such as in theabove FIG. 35 example and for 16M integration, are intended to befabricated to include more than {fraction (1/64)}th of the totaloperable memory cells of the finished memory device to contend withinoperable circuitry undesirably fabricated within the arrays.

[0121] However upon final fabrication and assembly, the respectivememory arrays are provided to contain {fraction (1/64)}th of the totalmemory cells of the memory device/chip. Accordingly, each array 160would have an area which is greater than the sum of {fraction (1/64)}thof the area which would be taken up by the total functional and operablyaddressable memory cells within the respective sub-array. Regardless,that surface area of the die which is consumed by the memory cells whichare finally functional and operably addressable through final fusing orother means will have a total combined area (although perhaps disjointedif internal inoperable cells are fused out) in this inventive examplewhich is no greater than 53 mm². However, the area consumed by arespective individual array 160 will be greater than {fraction (1/64)}thof the described 53 mm² due to the redundant circuitry. Sixty four (64)sub-arrays is the preferred number for 16M integration, while 256sub-arrays would be more preferred and typical for 64M integration.There will be areas on die 150 within at least one array 160 where atleast 100 square microns of continuous die surface area has a collectionof all operable memory cells, with no inoperable memory cells beingincluded within that particular 100 square micron area. In accordancewith one aspect of the invention, there will be at least 128 memorycells within such 100 square microns of continuous die surface area.

[0122] The above described preferred maximum 53 mm² area occupied byfinally functional and addressable memory cells on a die for 64Mintegration is with respect to the above described four or lesscomposite conductive line layers construction of FIG. 24. With such fourconductive line layers, the peripheral circuitry, the pitch circuitryand the memory arrays will have a total combined continuous surface areaon the die which is less than or equal to 106 mm².

[0123] Where five composite conductive line layers are utilized, the diearea consumed by all of the functional and operably addressable memorycells will have a reduced total combined area (although again, mostlikely non-continuous/disjointed) which is no greater than 40 mm² for64M integration. Further in such instance, the peripheral circuitry, thepitch circuitry and the memory arrays will have a total combinedcontinuous surface area on the die which is less than or equal to 93mm².

[0124] Further for the example five composite conductive line layersconstruction, there will be areas on die 150 within at least one array160 where at least 100 square microns of continuous die surface area hasa collection of all operable memory cells, with no inoperable memorycells being included within that particular 100 square micron area. Inaccordance with an aspect of the invention, there will be at least 170memory cells within such 100 square microns of continuous die surfacearea.

[0125] In accordance with another aspect of the invention and at the 16Mmemory cell integration level, a total of no more than 17,000,000(typically exactly 16,777,216) functional and operably addressablememory cells are provided by the multiple memory arrays 160. Theoccupied area of all of the functional and operably addressable memorycells on the die consumed within the multiple memory arrays will have atotal combined area which is no greater than 14 mm². Such is achievable,by way of example only and not by way of limitation, in the context of afour or less composite conductive line layers construction as describedabove with respect to example FIGS. 24 and 25. In such instance, theperiphery circuitry, the pitch circuitry and the memory arrays have atotal combined continuous surface area on the die which is less than orequal to 35 mm². Also, at least one of the memory arrays which containat least 100 square microns of continuous die surface area will have atleast 128 functional and operably addressable memory cells.

[0126] Where five composite conductive line layers are utilized, the diearea consumed by all of the functional and operably addressable memorycells will have a reduced total combined area (although again, mostlikely non-continuous/disjointed) which is no greater than 11 mm² for16M integration. Further in such instance, the peripheral circuitry, thepitch circuitry and the memory arrays will have a total combinedcontinuous surface area on the die which is less than or equal to 32mm². Further, at least one of the memory arrays which contain at least100 square microns of continuous die surface area will have at least 170functional and operably addressable memory cells.

[0127] For example with respect to the above described FIG. 35 depictionand a five composite conductive line layers construction, at the 16Mintegration level, each of the 64 memory arrays 160 would include 256K(truly 262,144) functional and operably addressable memory cells. Anexample ultimate dimension for chip 150 is 3.78 mm by 8.20 mm, resultingin a total continuous die area of 31.0 mm².

[0128] In accordance with another aspect of the invention and at the 4Mmemory cell integration level, a total of no more than 4,500,000(typically exactly 4,194,394) functional and operably addressable memorycells are provided by the multiple memory arrays 160. The occupied areaof all of the functional and operably addressable memory cells on thedie consumed within the multiple memory arrays will have a totalcombined area which is no greater than 3.3 mm². Such is achievable, byway of example only and not by way of limitation, in the context of afour or less composite conductive line layers construction as describedabove with respect to example FIGS. 24 and 25. In such instance, theperiphery circuitry, the pitch circuitry and the memory arrays have atotal combined continuous surface area on the die which is less than orequal to 11 mm². Also, at least one of the memory arrays which containat least 100 square microns of continuous die surface area will have atleast 128 functional and operably addressable memory cells.

[0129] Where five composite conductive line layers are utilized, the diearea consumed by all of the functional and operably addressable memorycells will have a reduced total combined area (although again, mostlikely non-continuous/disjointed) which is no greater than 2.5 mm² for4M integration. Further in such instance, the peripheral circuitry, thepitch circuitry and the memory arrays will have a total combinedcontinuous surface area on the die which is less than or equal to 10.2mm². Further, at least one of the memory arrays which contain at least100 square microns of continuous die surface area will have at least 170functional and operably addressable memory cells.

[0130] The above described products provide example memory circuitintegration at the 64M, 16M, and 4M integration levels utilizing lessdie surface area than has previously been achieved at such integrationlevels. Such can facilitate making the ultimate size of the resultantpackage smaller by making the integrated dies potentially smaller.Further for the manufacturer, more dies per wafer are capable of beingachieved thus increasing yield, thereby lowering manufacturing costs andincreasing profitability. Further, the higher memory cell densityenables lower operating power and greater speed with less parasiticcapacitance. Further, the word lines and digit lines can be shorter, andlower overall voltages can be utilized.

[0131] In accordance with another aspect of the invention, asemiconductor memory device includes a plurality of functional andoperably addressable memory cells arranged in multiple memory arraysformed on a semiconductor die; and circuitry formed on the semiconductordie permitting data to be written to and read from one or more of thememory cells, at least one of the memory arrays containing at least 100square microns of continuous die surface area having at least 170 of thefunctional and operably addressable memory cells. Preferably, the totalnumber of functional and operably addressable memory cells on thesemiconductor die is between 256,000,000 and 275,000,000.

[0132] In accordance with yet another aspect, a 256M semiconductormemory device comprises a semiconductor die encapsulated in a package,the package having an encapsulating body and electrically conductiveinterconnect pins extending outwardly from the body; a total of from256,000,000 to 275,000,000 functional and operably addressable memorycells arranged in multiple memory arrays formed on the die, theindividual functional and operably addressable memory cells occupyingarea on the die within the memory arrays, the occupied area of allfunctional and addressable memory cells on the die having a totalcombined area which is no greater than 157 mm²; and peripheral circuitryand pitch circuitry formed on the die relative to the memory arrays; theperipheral circuitry electrically interconnecting with the pins andincluding operably interconnected control and timing circuitry, addressand redundancy circuitry, data and test path circuitry, and voltagesupply circuitry which collectively enable full access to alladdressable memory cells of the memory arrays. The above 157 mm² ispreferably for at least a five composite conductive line layer process.Further preferably the peripheral circuitry, the pitch circuitry and thememory arrays have a total combined continuous surface area on the diewhich is less than or equal to 262 mm². The 262 mm² is also preferablyfor at least a five composite conductive line layer process.

[0133] Semiconductor wafer fabrication to produce memory chips or diesstrives to get as many dies from a wafer as possible. Such is approachedby trying to maximize the number of available die sites per wafer for agiven level of integration and still achieve acceptable overall yieldsof numbers of operable dies per wafer. Typically, not all of the wafersurface area is useable for fabrication of operable memory chips, norare all die sites on a given wafer fabricated to have respective memorychips.

[0134] For example, most all of the outermost wafer edge area is notuseable as such does not include sufficient respective surface area forindividual memory chips. This is due to, for example in part, therounded outer periphery of most of the wafer. Further, wafer mapping fordies typically starts at the very center and works outwardly, inherentlyleaving less than full desired area for memory chips around theoutermost wafer area. Accordingly, memory circuitry fabricated in theseoutermost sites will be incomplete and not useable. Further, a smallnumber of the available die sites on a wafer may not be designed to havememory circuitry therein. Such sites might, for example, be fabricatedto have test circuitry to facilitate testing of all chips on the waferfor operability prior to dicing. Regardless, it is desirable for thefabricator to maximize available die sites on the wafer in an effort tomaximize yield of operable product per wafer. In the context of thisdocument, “die sites” refers only to those areas on the wafer ofadequate size to enable retaining a fabricated memory chip of theselected integration, regardless of whether such area retains such amemory chip.

[0135] The size of the wafer of course impacts the number of die sitesavailable for memory circuitry, as does scribe line width, circuitdensity, and the number of memory cells per chip/die area. Wafers can bepurchased typically in 6″ and 8″, and soon 12″, major diameter sizes.The 6″ wafers have a single flat on the outermost peripheral wafer edge,whereas the 8″ wafer and the 12″ wafer in development have no flats. Forexample for a 6″ single-flat wafer at the 4M integration level, theknown prior art wafers have no more than 900 die sites per wafer. For an8″ no-flat wafer, the known 4M integration level prior art wafers haveno more than 1650 die sites per wafer. For a 12″ no-flat wafer, theknown 4M integration level prior art proposed wafers have no more than3900 die sites per wafer.

[0136] Further for a 6″ single-flat wafer at the 16M integration level,the known prior art wafers have no more than 250 die sites per wafer.For an 8″ no-flat wafer, the known 16M integration level prior artwafers have no more than 470 die sites per wafer. For a 12″ no-flatwafer, the known 16M integration level prior art proposed wafers have nomore than 1120 die sites per wafer.

[0137] Further for a 6″ single-flat wafer at the 64M integration level,the known prior art wafers have no more than 70 die sites per wafer. Foran 8″ no-flat wafer, the known 64M integration level prior art wafershave no more than 135 die sites per wafer. For a 12″ no-flat wafer, theknown 64M integration level prior art proposed wafers have no more than320 die sites per wafer.

[0138] In accordance with the invention, considerably greater numbers ofdie sites for wafers are achieved.

[0139] For example, a plurality of 4M semiconductor memory devices inaccordance with the invention comprises a processed semiconductor waferready for dicing having a major diameter of about 6 inches; and aplurality of die sites on the processed wafer, the die sites being sizedfor respective receipt of from 4,000,000 to 4,500,000 functional andoperably addressable memory cells arranged in multiple memory arrayswithin a respective die site, a predominate number of the total numberof die sites on the processed wafer being occupied by memory deviceshaving a plurality of functional and operably addressable memory cellsarranged in multiple memory arrays, the total number of die sites on theprocessed wafer being at least 1300. Actual number of die sitesachievable with the above example preferred four composite conductiveline layers process for a 6 inch wafer is 1382. Even more preferably,the number of die sites per processed 6 inch wafer is at least 1425, andstill even more preferably at least 1490. Actual number of die sitesachievable with the above example preferred five composite conductiveline layers process for a 6 inch wafer is 1494.

[0140]FIG. 36 illustrates an example single-flat wafer 555 having aplurality of die sites 556, including edge areas 557 of insufficientsize to constitute respective die sites.

[0141] Further, a plurality of 4M semiconductor memory devices inaccordance with the invention comprises a processed semiconductor waferready for dicing having a major diameter of about 8 inches; and aplurality of die sites on the processed wafer, the die sites being sizedfor respective receipt of from 4,000,000 to 4,500,000 functional andoperably addressable memory cells arranged in multiple memory arrayswithin a respective die site, a predominate number of the total numberof die sites on the processed wafer being occupied by memory deviceshaving a plurality of functional and operably addressable memory cellsarranged in multiple memory arrays, the total number of die sites on theprocessed wafer being at least 2500. Actual number of die sitesachievable with the above example preferred four composite conductiveline layers process for an 8 inch wafer is 2580. Even more preferably,the number of die sites per processed 8 inch wafer is at least 2700, andstill even more preferably at least 2775. Actual number of die sitesachievable with the above example preferred five composite conductiveline layers process for a processed 8 inch wafer is 2778.

[0142] Further, a plurality of 4M semiconductor memory devices inaccordance with the invention comprises a processed semiconductor waferready for dicing having a major diameter of about 12 inches; and aplurality of die sites on the processed wafer, the die sites being sizedfor respective receipt of from 4,000,000 to 4,500,000 functional andoperably addressable memory cells arranged in multiple memory arrayswithin a respective die site, a predominate number of the total numberof die sites on the processed wafer being occupied by memory deviceshaving a plurality of functional and operably addressable memory cellsarranged in multiple memory arrays, the total number of die sites on theprocessed wafer being at least 5975. Actual number of die sitesachievable with the above example preferred four composite conductiveline layers process for a 12 inch wafer is 6005. Even more preferably,the number of die sites per processed 12 inch wafer is at least 6400,and still even more preferably at least 6450. Actual number of die sitesachievable with the above example preferred five composite conductiveline layers process for a processed 12 inch wafer is 6460.

[0143] Further, a plurality of 16M semiconductor memory devices inaccordance with the invention comprises a processed semiconductor waferready for dicing having a major diameter of about 6 inches; and aplurality of die sites on the processed wafer, the die sites being sizedfor respective receipt of from 16,000,000 to 17,000,000 functional andoperably addressable memory cells arranged in multiple memory arrayswithin a respective die site, a predominate number of the total numberof die sites on the processed wafer being occupied by memory deviceshaving a plurality of functional and operably addressable memory cellsarranged in multiple memory arrays, the total number of die sites on theprocessed wafer being at least 375. Actual number of die sitesachievable with the above example preferred four composite conductiveline layers process for a 6 inch wafer is 413. Even more preferably, thenumber of die sites per processed 6 inch wafer is at least 425, andstill even more preferably at least 455. Actual number of die sitesachievable with the above example preferred five composite conductiveline layers process for a 6 inch wafer is 459.

[0144] Further, a plurality of 16M semiconductor memory devices inaccordance with the invention comprise a processed semiconductor waferready for dicing having a major diameter of about 8 inches; and aplurality of die sites on the processed wafer, the die sites being sizedfor respective receipt of from 16,000,000 to 17,000,000 functional andoperably addressable memory cells arranged in multiple memory arrayswithin a respective die site, a predominate number of the total numberof die sites on the processed wafer being occupied by memory deviceshaving a plurality of functional and operably addressable memory cellsarranged in multiple memory arrays, the total number of die sites on theprocessed wafer being at least 700. Actual number of die sitesachievable with the above example preferred four composite conductiveline layers process for an 8 inch wafer is 778. Even more preferably,the number of die sites per processed 8 inch wafer is at least 800, andstill even more preferably at least 855. Actual number of die sitesachievable with the above example preferred five composite conductiveline layers process for a processed 8 inch wafer is 860.

[0145] Further, a plurality of 16M semiconductor memory devices inaccordance with the invention comprises a processed semiconductor waferready for dicing having a major diameter of about 12 inches; and aplurality of die sites on the processed wafer, the die sites being sizedfor respective receipt of from 16,000,000 to 17,000,000 functional andoperably addressable memory cells arranged in multiple memory arrayswithin a respective die site, a predominate number of the total numberof die sites on the processed wafer being occupied by memory deviceshaving a plurality of functional and operably addressable memory cellsarranged in multiple memory arrays, the total number of die sites on theprocessed wafer being at least 1780. Actual number of die sitesachievable with the above example preferred four composite conductiveline layers process for a 12 inch wafer is 1843. Even more preferably,the number of die sites per processed 12 inch wafer is at least 1980,and still even more preferably at least 2015. Actual number of die sitesachievable with the above example preferred five composite conductiveline layers process for a processed 12 inch wafer is 2019.

[0146] Further, a plurality of 64M semiconductor memory devices inaccordance with the invention comprises a processed semiconductor waferready for dicing having a major diameter of about 6 inches; and aplurality of die sites on the processed wafer, the die sites being sizedfor respective receipt of from 64,000,000 to 68,000,000 functional andoperably addressable memory cells arranged in multiple memory arrayswithin a respective die site, a predominate number of the total numberof die sites on the processed wafer being occupied by memory deviceshaving a plurality of functional and operably addressable memory cellsarranged in multiple memory arrays, the total number of die sites on theprocessed wafer being at least 100. Actual number of die sitesachievable with the above example preferred four composite conductiveline layers process for a 6 inch wafer is 126. Even more preferably, thenumber of die sites per processed 6 inch wafer is at least 130, andstill even more preferably at least 145. Actual number of die sitesachievable with the above example preferred five composite conductiveline layers process for a 6 inch wafer is 146.

[0147] Further, a plurality of 64M semiconductor memory devices inaccordance with the invention comprises a processed semiconductor waferready for dicing having a major diameter of about 8 inches; and aplurality of die sites on the processed wafer, the die sites being sizedfor respective receipt of from 64,000,000 to 68,000,000 functional andoperably addressable memory cells arranged in multiple memory arrayswithin a respective die site, a predominate number of the total numberof die sites on the processed wafer being occupied by memory deviceshaving a plurality of functional and operably addressable memory cellsarranged in multiple memory arrays, the total number of die sites on theprocessed wafer being at least 200. Actual number of die sitesachievable with the above example preferred four composite conductiveline layers process for an 8 inch wafer is 244. Even more preferably,the number of die sites per processed 8 inch wafer is at least 250, andstill even more preferably at least 280. Actual number of die sitesachievable with the above example preferred five composite conductiveline layers process for a processed 8 inch wafer is 282.

[0148] Further, a plurality of 64M semiconductor memory devices inaccordance with the invention comprises a processed semiconductor waferready for dicing having a major diameter of about 12 inches; and aplurality of die sites on the processed wafer, the die sites being sizedfor respective receipt of from 64,000,000 to 68,000,000 functional andoperably addressable memory cells arranged in multiple memory arrayswithin a respective die site, a predominate number of the total numberof die sites on the processed wafer being occupied by memory deviceshaving a plurality of functional and operably addressable memory cellsarranged in multiple memory arrays, the total number of die sites on theprocessed wafer being at least 525. Actual number of die sitesachievable with the above example preferred four composite conductiveline layers process for a 12 inch wafer is 585. Even more preferably,the number of die sites per processed 12 inch wafer is at least 625, andstill even more preferably at least 670. Actual number of die sitesachievable with the above example preferred five composite conductiveline layers process for a processed 12 inch wafer is 674.

[0149] Still further, a plurality of 256M semiconductor memory devicesin accordance with the invention comprises a processed semiconductorwafer ready for dicing having a major diameter of about 6 inches; and aplurality of die sites on the processed wafer, the die sites being sizedfor respective receipt of from 256,000,000 to 275,000,000 functional andoperably addressable memory cells arranged in multiple memory arrayswithin a respective die site, a predominate number of the total numberof die sites on the processed wafer being occupied by memory deviceshaving a plurality of functional and operably addressable memory cellsarranged in multiple memory arrays, the total number of die sites on theprocessed wafer being at least 45. Actual number of die sites achievablewith the above example preferred five composite conductive line layersprocess for a processed 6 inch wafer is 47.

[0150] Further, a plurality of 256M semiconductor memory devices inaccordance with the invention comprises a processed semiconductor waferready for dicing having a major diameter of about 8 inches; and aplurality of die sites on the processed wafer, the die sites being sizedfor respective receipt of from 256,000,000 to 275,000,000 functional andoperably addressable memory cells arranged in multiple memory arrayswithin a respective die site, a predominate number of the total numberof die sites on the processed wafer being occupied by memory deviceshaving a plurality of functional and operably addressable memory cellsarranged in multiple memory arrays, the total number of die sites on theprocessed wafer being at least 86. Actual number of die sites achievablewith the above example preferred five composite conductive line layersprocess for a 8 inch wafer is 89.

[0151] Further, a plurality of 256M semiconductor memory devices inaccordance with the invention comprises a processed semiconductor waferready for dicing having a major diameter of about 12 inches; and aplurality of die sites on the processed wafer, the die sites being sizedfor respective receipt of from 256,000,000 to 275,000,000 functional andoperably addressable memory cells arranged in multiple memory arrayswithin a respective die site, a predominate number of the total numberof die sites on the processed wafer being occupied by memory deviceshaving a plurality of functional and operably addressable memory cellsarranged in multiple memory arrays, the total number of die sites on theprocessed wafer being at least 210. Even more preferably, the number ofdie sites per processed 12 inch wafer is at least 225. Actual number ofdie sites achievable with the above example preferred five compositeconductive line layers process for a 12 inch wafer is 228.

[0152] In compliance with the statute, the invention has been describedin language more or less specific as to structural and methodicalfeatures. It is to be understood, however, that the invention is notlimited to the specific features shown and described, since the meansherein disclosed comprise preferred forms of putting the invention intoeffect. The invention is, therefore, claimed in any of its forms ormodifications within the proper scope of the appended claimsappropriately interpreted in accordance with the doctrine ofequivalents.

1. A semiconductor memory device comprising: a plurality of functionaland operably addressable memory cells arranged in multiple memory arraysformed on a semiconductor die; and circuitry formed on the semiconductordie permitting data to be written to and read from one or more of thememory cells, at least one of the memory arrays containing at least 100square microns of continuous die surface area having at least 170 of thefunctional and operably addressable memory cells.
 2. The semiconductormemory device of claim 1 wherein the total number of functional andoperably addressable memory cells on the semiconductor die is no morethan 275,000,000.
 3. The semiconductor memory device of claim 1 whereinthe total number of functional and operably addressable memory cells onthe semiconductor die is between 256,000,000 and 275,000,000.
 4. A 256Msemiconductor memory device comprising: a semiconductor die encapsulatedin a package, the package having an encapsulating body and electricallyconductive interconnect pins extending outwardly from the body; a totalof from 256,000,000 to 275,000,000 functional and operably addressablememory cells arranged in multiple memory arrays formed on the die, theindividual functional and operably addressable memory cells occupyingarea on the die within the memory arrays, the occupied area of allfunctional and addressable memory cells on the die having a totalcombined area which is no greater than 157 mm²; and peripheral circuitryand pitch circuitry formed on the die relative to the memory arrays; theperipheral circuitry electrically interconnecting with the pins andincluding operably interconnected control and timing circuitry, addressand redundancy circuitry, data and test path circuitry, and voltagesupply circuitry which collectively enable full access to alladdressable memory cells of the memory arrays.
 5. The semiconductormemory device of claim 4 wherein the peripheral circuitry, the pitchcircuitry, and the memory arrays are fabricated to include at least fivecomposite conductive line layers.
 6. The semiconductor memory device ofclaim 4 wherein the peripheral circuitry, the pitch circuitry and thememory arrays having a total combined continuous surface area on the diewhich is less than or equal to 262 mm².
 7. The semiconductor memorydevice of claim 4 wherein the peripheral circuitry, the pitch circuitry,and the memory arrays are fabricated to include at least five compositeconductive line layers; the peripheral circuitry, the pitch circuitryand the memory arrays having a total combined continuous surface area onthe die which is less than or equal to 262 mm².
 8. A plurality of 4Msemiconductor memory devices comprising: a processed semiconductor waferready for dicing having a major diameter of about 6 inches; and aplurality of die sites on the processed wafer, the die sites being sizedfor respective receipt of from 4,000,000 to 4,500,000 functional andoperably addressable memory cells arranged in multiple memory arrayswithin a respective die site, a predominate number of the total numberof die sites on the processed wafer being occupied by memory deviceshaving a plurality of functional and operably addressable memory cellsarranged in multiple memory arrays, the total number of die sites on theprocessed wafer being at least
 1300. 9. The plurality of semiconductormemory devices of claim 8 wherein the total number of die sites on theprocessed wafer is at least
 1425. 10. The plurality of semiconductormemory devices of claim 8 wherein the total number of die sites on theprocessed wafer is at least
 1490. 11. A plurality of 4M semiconductormemory devices comprising: a processed semiconductor wafer ready fordicing having a major diameter of about 8 inches; and a plurality of diesites on the processed wafer, the die sites being sized for respectivereceipt of from 4,000,000 to 4,500,000 functional and operablyaddressable memory cells arranged in multiple memory arrays within arespective die site, a predominate number of the total number of diesites on the processed wafer being occupied by memory devices having aplurality of functional and operably addressable memory cells arrangedin multiple memory arrays, the total number of die sites on theprocessed wafer being at least
 2500. 12. The plurality of semiconductormemory devices of claim 11 wherein the total number of die sites on theprocessed wafer is at least
 2700. 13. The plurality of semiconductormemory devices of claim 11 wherein the total number of die sites on theprocessed wafer is at least
 2775. 14. A plurality of 4M semiconductormemory devices comprising: a processed semiconductor wafer ready fordicing having a major diameter of about 12 inches; and a plurality ofdie sites on the processed wafer, the die sites being sized forrespective receipt of from 4,000,000 to 4,500,000 functional andoperably addressable memory cells arranged in multiple memory arrayswithin a respective die site, a predominate number of the total numberof die sites on the processed wafer being occupied by memory deviceshaving a plurality of functional and operably addressable memory cellsarranged in multiple memory arrays, the total number of die sites on theprocessed wafer being at least
 5975. 15. The plurality of semiconductormemory devices of claim 14 wherein the total number of die sites on theprocessed wafer is at least
 6400. 16. The plurality of semiconductormemory devices of claim 14 wherein the total number of die sites on theprocessed wafer is at least
 6450. 17. A plurality of 16M semiconductormemory devices comprising: a processed semiconductor wafer ready fordicing having a major diameter of about 6 inches; and a plurality of diesites on the processed wafer, the die sites being sized for respectivereceipt of from 16,000,000 to 17,000,000 functional and operablyaddressable memory cells arranged in multiple memory arrays within arespective die site, a predominate number of the total number of diesites on the processed wafer being occupied by memory devices having aplurality of functional and operably addressable memory cells arrangedin multiple memory arrays, the total number of die sites on theprocessed wafer being at least
 375. 18. The plurality of semiconductormemory devices of claim 17 wherein the total number of die sites on theprocessed wafer is at least
 425. 19. The plurality of semiconductormemory devices of claim 17 wherein the total number of die sites on theprocessed wafer is at least
 455. 20. A plurality of 16M semiconductormemory devices comprising: a processed semiconductor wafer ready fordicing having a major diameter of about 8 inches; and a plurality of diesites on the processed wafer, the die sites being sized for respectivereceipt of from 16,000,000 to 17,000,000 functional and operablyaddressable memory cells arranged in multiple memory arrays within arespective die site, a predominate number of the total number of diesites on the processed wafer being occupied by memory devices having aplurality of functional and operably addressable memory cells arrangedin multiple memory arrays, the total number of die sites on theprocessed wafer being at least
 700. 21. The plurality of semiconductormemory devices of claim 20 wherein the total number of die sites on theprocessed wafer is at least
 800. 22. The plurality of semiconductormemory devices of claim 20 wherein the total number of die sites on theprocessed wafer is at least
 855. 23. A plurality of 16M semiconductormemory devices comprising: a processed semiconductor wafer ready fordicing having a major diameter of about 12 inches; and a plurality ofdie sites on the processed wafer, the die sites being sized forrespective receipt of from 16,000,000 to 17,000,000 functional andoperably addressable memory cells arranged in multiple memory arrayswithin a respective die site, a predominate number of the total numberof die sites on the processed wafer being occupied by memory deviceshaving a plurality of functional and operably addressable memory cellsarranged in multiple memory arrays, the total number of die sites on theprocessed wafer being at least
 1780. 24. The plurality of semiconductormemory devices of claim 23 wherein the total number of die sites on theprocessed wafer is at least
 1980. 25. The plurality of semiconductormemory devices of claim 23 wherein the total number of die sites on theprocessed wafer is at least
 2015. 26. A plurality of 64M semiconductormemory devices comprising: a processed semiconductor wafer ready fordicing having a major diameter of about 6 inches; and a plurality of diesites on the processed wafer, the die sites being sized for respectivereceipt of from 64,000,000 to 68,000,000 functional and operablyaddressable memory cells arranged in multiple memory arrays within arespective die site, a predominate number of the total number of diesites on the processed wafer being occupied by memory devices having aplurality of functional and operably addressable memory cells arrangedin multiple memory arrays, the total number of die sites on theprocessed wafer being at least
 100. 27. The plurality of semiconductormemory devices of claim 26 wherein the total number of die sites on theprocessed wafer is at least
 130. 28. The plurality of semiconductormemory devices of claim 26 wherein the total number of die sites on theprocessed wafer is at least
 145. 29. A plurality of 64M semiconductormemory devices comprising: a processed semiconductor wafer ready fordicing having a major diameter of about 8 inches; and a plurality of diesites on the processed wafer, the die sites being sized for respectivereceipt of from 64,000,000 to 68,000,000 functional and operablyaddressable memory cells arranged in multiple memory arrays within arespective die site, a predominate number of the total number of diesites on the processed wafer being occupied by memory devices having aplurality of functional and operably addressable memory cells arrangedin multiple memory arrays, the total number of die sites on theprocessed wafer being at least
 200. 30. The plurality of semiconductormemory devices of claim 29 wherein the total number of die sites on theprocessed wafer is at least
 250. 31. The plurality of semiconductormemory devices of claim 29 wherein the total number of die sites on theprocessed wafer is at least
 280. 32. A plurality of 64M semiconductormemory devices comprising: a processed semiconductor wafer ready fordicing having a major diameter of about 12 inches; and a plurality ofdie sites on the processed wafer, the die sites being sized forrespective receipt of from 64,000,000 to 68,000,000 functional andoperably addressable memory cells arranged in multiple memory arrayswithin a respective die site, a predominate number of the total numberof die sites on the processed wafer being occupied by memory deviceshaving a plurality of functional and operably addressable memory cellsarranged in multiple memory arrays, the total number of die sites on theprocessed wafer being at least
 525. 33. The plurality of semiconductormemory devices of claim 32 wherein the total number of die sites on theprocessed wafer is at least
 625. 34. The plurality of semiconductormemory devices of claim 32 wherein the total number of die sites on theprocessed wafer is at least
 670. 35. A plurality of 256M semiconductormemory devices comprising: a processed semiconductor wafer ready fordicing having a major diameter of about 6 inches; and a plurality of diesites on the processed wafer, the die sites being sized for respectivereceipt of from 256,000,000 to 275,000,000 functional and operablyaddressable memory cells arranged in multiple memory arrays within arespective die site, a predominate number of the total number of diesites on the processed wafer being occupied by memory devices having aplurality of functional and operably addressable memory cells arrangedin multiple memory arrays, the total number of die sites on theprocessed wafer being at least
 45. 36. The plurality of semiconductormemory devices of claim 35 wherein the total number of die sites on theprocessed wafer is at least
 47. 37. A plurality of 256M semiconductormemory devices comprising: a processed semiconductor wafer ready fordicing having a major diameter of about 8 inches; and a plurality of diesites on the processed wafer, the die sites being sized for respectivereceipt of from 256,000,000 to 275,000,000 functional and operablyaddressable memory cells arranged in multiple memory arrays within arespective die site, a predominate number of the total number of diesites on the processed wafer being occupied by memory devices having aplurality of functional and operably addressable memory cells arrangedin multiple memory arrays, the total number of die sites on theprocessed wafer being at least
 86. 38. The plurality of semiconductormemory devices of claim 37 wherein the total number of die sites on theprocessed wafer is at least
 89. 39. A plurality of 256M semiconductormemory devices comprising: a processed semiconductor wafer ready fordicing having a major diameter of about 12 inches; and a plurality ofdie sites on the processed wafer, the die sites being sized forrespective receipt of from 256,000,000 to 275,000,000 functional andoperably addressable memory cells arranged in multiple memory arrayswithin a respective die site, a predominate number of the total numberof die sites on the processed wafer being occupied by memory deviceshaving a plurality of functional and operably addressable memory cellsarranged in multiple memory arrays, the total number of die sites on theprocessed wafer being at least
 210. 40. The plurality of semiconductormemory devices of claim 39 wherein the total number of die sites on theprocessed wafer is at least 225.